A <inline-formula> <tex-math notation="LaTeX">2 \times 2 </tex-math></inline-formula> dual-polarized antenna subarray with filtering responses is proposed in this paper. This antenna subarray is a multilayered 3-D geometry, including a dual-path <inline-formula> <tex-math notation="LaTeX">1 \times 4 </tex-math></inline-formula> feeding network and four cavity-backed slot antennas. The isolation performance between two input ports is greatly improved by a novel method, which only needs to modify several vias in a square resonator. Cavities in the feeding network are properly arranged and coupled using different coupling structures, so that the operation modes in each cavity for different paths can always remain orthogonal, which enables the subarray to exhibit not only filtering functions (in both reflection coefficients and gain responses), but also a low cross-polarization level. A prototype is fabricated with a center frequency of 37 GHz and a bandwidth of 600 MHz for demonstration. Good agreement is achieved between simulation and measurement, for both <inline-formula> <tex-math notation="LaTeX">S </tex-math></inline-formula>-parameter and far-field results. The proposed filtering dual-polarized antenna array is very suitable to be employed as the subarray in millimeter-wave 5G base stations to reduce the complexity and integration loss of such beamforming systems.

In this paper, coaxial through-silicon via (C-TSV) is modeled and studied with the consideration of electrically floating inner silicon substrate. Nonlinear capacitances of the central via and the outer shielding shell are accurately captured by solving cylindrical Poisson equation. By employing symbolically defined device block, the nonlinear capacitances of the C-TSV with electrically floating inner silicon are combined into the equivalent circuit model, and their impacts on the electrical characteristics are examined.

We developed a chip mounting technology suitable for low-cost assemblies in the 300-500-GHz frequency range, compatible with standard chip and submount fabrication techniques. The waveguide and transition designs are compatible with indium phosphide heterobipolar transistor millimeter-wave monolithic integrated circuit chip architecture. Increased conductor shielding in different multilayer thin-film waveguide topologies is applied to suppress radiative losses, enabling low-loss interconnects up to 500-GHz bandwidth. Standard flip-chip align-and-place equipment is used to assemble the chips onto submounts. Losses are evaluated by banded <inline-formula> <tex-math notation="LaTeX">{S} </tex-math></inline-formula>-parameter measurements between 10 MHz and 500 GHz. For an optimized stripline-to-stripline transition, an insertion loss of less than 1 dB was measured at 500 GHz.

The contribution of this paper is to propose novel balanced and dual-band bandpass filters (BPFs), using quarter-mode (QM) and eighth-mode (EM) substrate integrated waveguide (SIW) cavities, for the size reduction of the overall circuit. Two balanced BPFs, which separately demonstrate a third-order Chebyshev response and a fourth-order quasi-elliptic response, are realized by properly choosing, feeding, and coupling those QMSIW and EMSIW cavities. Not only desired differential-mode operation within the passband, but also good common-mode suppression in a certain frequency range have been achieved. Furthermore, a dual-band BPF with improved out-of-band rejection is also realized by properly constructing the coupling topology of four EMSIW cavities. An additional source-to-load coupling path is introduced in this dual-band BPF to obtain more transmission zeros (TZs). The sizes of resonant cavities utilized in the above designs are only one-fourth or one-eighth of those rectangular ones in conventional designs, which lead to a significant reduction in the overall circuit size. All proposed designs have been fabricated and measured to verify simulation predictions. Based on the author's knowledge, it is the first time using QMSIW and EMSIW for balanced filter designs, and dual-band filter designs with TZs.

In order to attain high speed and high precision in modern electronic coating, an internal-mix airblast spray-coating valve was designed. The device used a reciprocating piston to control the supply of liquid, which was mixed with gas in the atomization chamber and was sprayed out from the nozzle. The movement of gas and liquid in the spraying nozzle was first analyzed. The structural parameters of the spraying nozzle are designed and optimized via finite element software. Finally, the experimental platform was set up to test the performance of the optimized spray-coating valve. Results show that supply pressures of atomizing gas and fluid all directly affect the coating layer width and thickness, and that the spraying regularity between them was obtained. When the fluid viscosity, atomizing air pressure, fluid supply pressure, and spraying height were 200 cps, 30 kpa, 20 kpa, and 8 mm, respectively, the rate of the moving platform was 100 mm/s, the length of the coating layer was 100 mm, the coating layer width was 9.4 mm, the coating layer thickness was <inline-formula> <tex-math notation="LaTeX">230~\mu \text{m} </tex-math></inline-formula>, and the average coating mass was 186 mg. The accuracy of the coating mass can be controlled at less than 5%.

Thermomechanical reliability of copper-plated through-package vias (TPVs) in ultrathin bare glass interposers was investigated through modeling, design, fabrication, reliability characterization, and failure analysis. Finite-element models were developed to analyze stress and strain distribution in TPV structures, and to obtain design guidelines for reliable TPVs. In order to experimentally validate the predictions of simulations, bare glass substrates of 100 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> thickness with vias of 30 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> diameter at 120 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> pitch were metallized using Ti/Cu sputtering, followed by patterning and electroplating. Cu TPV daisy chains were fabricated and subjected to thermal cycling test between ?55 °C and 125 °C to assess their thermomechanical reliability. Detailed cross-sectional analysis was also carried out by scanning electron microscope imaging of TPV cross sections. No electrical failures were detected in the Cu TPV chains. Failure analysis revealed copper delamination and crack formation in glass. The experimental reliability results are consistent with the thermomechanical models. Design and process recommendations are provided based on the modeling and experimental results.

IEEE transactions on components, packaging, and manufacturing technology
ISSN：2156-3950 volume：7 Issue：6 page：882-892
Murray, Bruce T
;
Schneebeli, Ken
;
Alissa, Husam A
;
Sammakia, Bahgat
;
Nemati, Kourosh

The accelerated growth of heat load in high-density data centers presents challenges to the design of effective cooling solutions. Both energy efficiency and the information technology (IT) equipment reliability are key requirements. Localized hybrid air-water cooling systems such as Rear Door Heat eXchangers (RDHXs) are an effective means to achieve these requirements. In this paper, the transient aerodynamic and thermal performance of a commercial RDHX was investigated experimentally. The RDHX was attached to an isolated server cabinet with a controllable heat load. A localized containment system was used to direct the airflow to the equipment in the cabinet that emanates from a single perforated tile within the enclosure. The water flow rate and supply water temperature to the RDHX was controlled, and a grid of 36 air velocity/temperature sensors was employed to monitor the airside of the cooling system. The cooling performance of the RDHX in an air blower failure scenario was investigated. The failure scenario was designed to diminish different parts of the overall system. The impact on the IT equipment and the cabinet outlet temperatures was assessed. Also, there was a significant reduction in the airflow to the IT equipment. The impact of the reduced airflow on different parts of the cabinet as well as the cooling performance of the heat exchanger was characterized during both failure and recovery.

This paper presents an accurate and efficient on-wafer calibration algorithm of broadband scattering-parameter measurements for radio-frequency integrated circuit production test applications. Three on-chip calibration standards with the same probe positions as those of the devices under test (DUTs) were designed to take advantage of fixed probe heads in the x-y directions during calibration and measurements. In addition, three on-chip standards-a series resistor and a shunt resistor (both of which have an offset line segment) as well as a transmission line (TL)-do not have to be characterized in advance, and the measurement reference impedance can be acquired further though self-calibration without an impedance-standard substrate (ISS). Simulation studies and experimental confirmation were conducted on GaAs substrates, from 2 to 110 GHz, in addition to comparisons of the multiline thru-reflect-line (TRL) calibration results.

This paper reports on one of the first demonstrations of the formation and metallization of 2-5-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8-15-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>-thick dry-film dielectrics were formed by 308-nm excimer laser ablation, followed by the metallization of the trenches and vias by copper electrodeposition. A low-cost planarization process was used to remove the copper overburden with a surface planer tool. Using an optimized set of materials and processes, multilayer redistribution layers with 2-<inline-formula> <tex-math notation="LaTeX">5~\mu \text{m} </tex-math></inline-formula> trenches and vias were successfully demonstrated. Although thin film processes on silicon wafers have been able to achieve 40-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> I/O pitch for interposers, the materials and processes integrated in this paper are scalable to large panel fabrication at much higher throughput, for interposers and high-density fan-out packaging at lower cost and higher performance than silicon interposers.

IEEE transactions on components, packaging, and manufacturing technology
ISSN：2156-3950 volume：7 Issue：6 page：925-935
Park, Junyong
;
Kim, Youngwoo
;
Orlandi, Antonio
;
Kim, Jonghoon J
;
Lim, Jaemin

We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.