This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of $$-\,2$$ - 2 . Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is +?2/??1 LSB and the INL is +?1.8/??1.4 LSB, respectively. Under an 8-bit resolution and a 62.5?Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is $$1.6\,\upmu$$ 1.6 μ A under a 2.5?V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of $$400 \times 500\,{\mathrm{mm}}^2$$ 400 × 500 mm 2 .;This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of -2. Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is +?2/??1 LSB and the INL is +?1.8/??1.4 LSB, respectively. Under an 8-bit resolution and a 62.5?Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is 1.6μA under a 2.5?V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of 400×500mm2.;This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of -2. Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is +?2/??1 LSB and the INL is +?1.8/??1.4 LSB, respectively. Under an 8-bit resolution and a 62.5?Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is 1.6μA under a 2.5?V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of 400×500mm2.

IEEE transactions on components, packaging, and manufacturing technology
ISSN：2156-3950 volume：8 Issue：4 page：519-530
Song, Jinwook
;
Kim, Subin
;
Park, Shinyoung
;
Kim, Joungho
;
Kim, Youngwoo

In this paper, we first propose a modeling method of arbitrary-shaped multilayer printed circuit board (PCB) ground planes and chassis of smartphones in the audio frequency range (20 Hz-20 kHz). The model is proposed to quickly and accurately analyze audio frequency ground voltage noise at an audio circuit that is induced from a time-division multiple access (TDMA) RF power amplifier (PA) while it is switching at an audio frequency during a call. Conventional 3-D electromagnetic (EM) simulation consumes enormous computation time and resources. However, the proposed method models the ground network as a resistive ground distribution network based on the finite-difference method and saves the computation time and resources. We verified the proposed modeling method by comparing ground noise coupling levels obtained from the proposed model, 3-D EM simulation, and measurement in the time and audio frequency domains. The proposed model showed 3.4% and 22.8% differences in the time domain and 3.8% and 14.8% differences at the 217-Hz fundamental frequency in the frequency domain, respectively, compared to 3-D EM simulation and measurement. Furthermore, we used the proposed model to analyze the ground noise coupling between audio circuits and TDMA RF PAs integrated on various designs of PCBs. To verify the correlation between the analysis and the actual performance degradation of audio circuits, we fabricated the PCBs, mounted commercial audio Delta-Sigma modulators and RF PAs, and measured the output of the modulators. The correlation is verified from the modulator on the PCB with the least ground noise coupling showing a spurious-free dynamic range 40.5 dB higher than the modulator on the PCB with the largest ground noise coupling.

Embedded inductors in ultrathin glass substrates were modeled, designed, fabricated, and characterized. Various 2-D and 3-D topologies were explored to obtain the tradeoffs in inductance density, quality (<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>) factor, size, and self-resonant frequency (SRF). Single-layer spiral inductors were modeled and designed to formulate an inductor library that is optimized for high inductance densities. These include variations in the number of turns, conductor linewidth and spacing, and the ratios of inner diameter and outer diameter of the spiral. In order to optimize the inductor topology for higher <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula> factors, various types of 3-D topologies with 300-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> glass were studied through modeling, fabrication, and model validation. Inductance densities, <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>, and SRF were measured for various topologies. Higher inductance densities of 10-20 nH/mm 2 with a <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula> factor of 30-40 are obtained for spiral inductors on glass, making them more suitable for module miniaturization when <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>-factor requirements are not stringent. For higher <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula> factors, 3-D solenoid and daisy-chain topologies are found to be more suitable in spite of their low inductance densities of 3 nH/mm 2 , making them a better choice for applications where better channel selectivity, precise phase-switching, and lower insertion loss are needed.

IEEE transactions on components, packaging, and manufacturing technology
ISSN：2156-3950 volume：8 Issue：3 page：439-446
Xiaolin Li
;
Lijun Wang
;
Jing Lin
;
Shenli Jia

Switchgear is an important power system protection equipment. Internal overheating of high-current switchgear has become the most common problem in the power system. In this paper, two different methods of simulation model are adopted to study the temperature rise issues of the 12-kV medium voltage switchgear. First, the electromagnetic field is calculated by using ANSYS APDL, then coupling with fluid dynamics software CFX to give the temperature and flow field distribution of the switchgear. Second, FLUENT and Maxwell 3-D are used to get the temperature and flow field distribution. It can be proven that CFX simulation of flow field is more suitable for the complex models. In the meantime, it has huge differences with FLUENT software when the temperature rise of the switchgear is calculated. In this paper, the influences of inlet velocity, the number of ventilation holes, and their positions are further studied, which could provide theoretical guidance for reducing temperature rise of the switchgear.

In this paper, we develop processes for printing 3-D structures by microdispensing materials loaded with dielectric and magnetic powders. Manufacturing with these materials is demonstrated by 3-D printing simple tower and bridge structures. The dielectric and magnetic properties are adjusted by loading different amounts of powder into a host silicone material. The long-term goal of the research is to print larger and more complex structures while also realizing a range of electromagnetic properties for applications in 3-D printed electromagnetics.

This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n?+?1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.;This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n?+?1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.;This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n?+?1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.

A reconfigurable noise-shaping time-to-digital converter (TDC) with adjustable resolution and input range is presented as a solution to nonlinear multi-input readout systems. By varying the frequency of a multi-step quantizer gated-ring oscillator (MSQ-GRO), the resolution and input range are adjusted without affecting the acquisition time. A prototype of a standalone second-order MASH MSQ-GRO-TDC operating over a 34?μs adjustable input range and covering five resolution modes is presented. The MSQ-GRO frequency changes by a factor of approximately 2, thus adjusting the resolution in steps of 0.5-bit. With a 12?MHz sampling frequency, the MSQ-GRO-TDC consumes 0.85 mW from a 1.2?V supply and achieves integrated noise of 42.8 and 1.9?psrms in 500 and 1?kHz bandwidths, respectively. The measured resolution is 13.3-to-15.3 bits with a sampling signal of 200?kHz in a 5?kHz bandwidth. The input range/resolution optimization allows up to 51% of power saving under the same supply voltage, thus extending the battery lifetime in portable devices. The MSQ-GRO-TDC is used as a data converter for a nonlinear pressure sensor. It achieves a worst-case resolution of 24.5?μbarrms. It is realized in a standard 0.13?μm CMOS technology and occupies an area of 0.145?mm2.;A reconfigurable noise-shaping time-to-digital converter (TDC) with adjustable resolution and input range is presented as a solution to nonlinear multi-input readout systems. By varying the frequency of a multi-step quantizer gated-ring oscillator (MSQ-GRO), the resolution and input range are adjusted without affecting the acquisition time. A prototype of a standalone second-order MASH MSQ-GRO-TDC operating over a 34?μs adjustable input range and covering five resolution modes is presented. The MSQ-GRO frequency changes by a factor of approximately $$\sqrt 2$$ 2 , thus adjusting the resolution in steps of 0.5-bit. With a 12?MHz sampling frequency, the MSQ-GRO-TDC consumes 0.85 mW from a 1.2?V supply and achieves integrated noise of 42.8 and 1.9?psrms in 500 and 1?kHz bandwidths, respectively. The measured resolution is 13.3-to-15.3 bits with a sampling signal of 200?kHz in a 5?kHz bandwidth. The input range/resolution optimization allows up to 51% of power saving under the same supply voltage, thus extending the battery lifetime in portable devices. The MSQ-GRO-TDC is used as a data converter for a nonlinear pressure sensor. It achieves a worst-case resolution of 24.5?μbarrms. It is realized in a standard 0.13?μm CMOS technology and occupies an area of 0.145?mm2.;A reconfigurable noise-shaping time-to-digital converter (TDC) with adjustable resolution and input range is presented as a solution to nonlinear multi-input readout systems. By varying the frequency of a multi-step quantizer gated-ring oscillator (MSQ-GRO), the resolution and input range are adjusted without affecting the acquisition time. A prototype of a standalone second-order MASH MSQ-GRO-TDC operating over a 34?μs adjustable input range and covering five resolution modes is presented. The MSQ-GRO frequency changes by a factor of approximately 2, thus adjusting the resolution in steps of 0.5-bit. With a 12?MHz sampling frequency, the MSQ-GRO-TDC consumes 0.85 mW from a 1.2?V supply and achieves integrated noise of 42.8 and 1.9?psrms in 500 and 1?kHz bandwidths, respectively. The measured resolution is 13.3-to-15.3 bits with a sampling signal of 200?kHz in a 5?kHz bandwidth. The input range/resolution optimization allows up to 51% of power saving under the same supply voltage, thus extending the battery lifetime in portable devices. The MSQ-GRO-TDC is used as a data converter for a nonlinear pressure sensor. It achieves a worst-case resolution of 24.5?μbarrms. It is realized in a standard 0.13?μm CMOS technology and occupies an area of 0.145?mm2.

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
ISSN：0925-1030 volume：95 Issue：1 page：1-16
Borrell, Jordan A
;
Frost, Shawn B
;
Dunham, Caleb
;
Barbay, Scott
;
Nudo, Randolph J

This paper reports on a fully miniaturized brain-spinal interface system for closed-loop cortically-controlled intraspinal microstimulation (ISMS). Fabricated in AMS 0.35?μm two-poly four-metal complementary metal–oxide–semiconductor technology, this system-on-chip measures ~?3.46?mm?×?3.46?mm and incorporates two identical 4-channel modules, each comprising a spike-recording front-end, embedded digital signal processing (DSP) unit, and programmable stimulating back-end. The DSP unit is capable of generating multichannel trigger signals for a wide array of ISMS triggering patterns based on real-time discrimination of a programmable number of intracortical neural spikes within a pre-specified time-bin duration via thresholding and user-adjustable time–amplitude windowing. The system is validated experimentally using an anesthetized rat model of a spinal cord contusion injury at the T8 level. Multichannel neural spikes are recorded from the cerebral cortex and converted in real time into electrical stimuli delivered to the lumbar spinal cord below the level of the injury, resulting in distinct patterns of hindlimb muscle activation.;This paper reports on a fully miniaturized brain-spinal interface system for closed-loop cortically-controlled intraspinal microstimulation (ISMS). Fabricated in AMS 0.35?μm two-poly four-metal complementary metal–oxide–semiconductor technology, this system-on-chip measures ~?3.46?mm?×?3.46?mm and incorporates two identical 4-channel modules, each comprising a spike-recording front-end, embedded digital signal processing (DSP) unit, and programmable stimulating back-end. The DSP unit is capable of generating multichannel trigger signals for a wide array of ISMS triggering patterns based on real-time discrimination of a programmable number of intracortical neural spikes within a pre-specified time-bin duration via thresholding and user-adjustable time–amplitude windowing. The system is validated experimentally using an anesthetized rat model of a spinal cord contusion injury at the T8 level. Multichannel neural spikes are recorded from the cerebral cortex and converted in real time into electrical stimuli delivered to the lumbar spinal cord below the level of the injury, resulting in distinct patterns of hindlimb muscle activation.;This paper reports on a fully miniaturized brain-spinal interface system for closed-loop cortically-controlled intraspinal microstimulation (ISMS). Fabricated in AMS 0.35?μm two-poly four-metal complementary metal–oxide–semiconductor technology, this system-on-chip measures ~?3.46?mm?×?3.46?mm and incorporates two identical 4-channel modules, each comprising a spike-recording front-end, embedded digital signal processing (DSP) unit, and programmable stimulating back-end. The DSP unit is capable of generating multichannel trigger signals for a wide array of ISMS triggering patterns based on real-time discrimination of a programmable number of intracortical neural spikes within a pre-specified time-bin duration via thresholding and user-adjustable time–amplitude windowing. The system is validated experimentally using an anesthetized rat model of a spinal cord contusion injury at the T8 level. Multichannel neural spikes are recorded from the cerebral cortex and converted in real time into electrical stimuli delivered to the lumbar spinal cord below the level of the injury, resulting in distinct patterns of hindlimb muscle activation.

The subject of this paper is the fault diagnosis of analog circuits based on the use of nullor concept. The fault location technique presented in the paper can be implemented in the general-purpose analysis program which provides many advantages, of which the most important is the automation of the diagnosis process. A simulation based diagnosis model can be obtained by introducing the norators across the potentially faulty elements and the fixators at the accessible nodes. A practical problem that arises when using this nullor diagnosis model is a lack of an efficient procedure for localization of multiple faults. In the proposed diagnosis technique, the online computational requirements are reduced by introducing a diagnosis model that contains accessible nodes only. The diagnosis model is obtained from the original circuit using relationships among the measured voltages and compensated currents of the faulty elements. The proposed faulty location technique is validated on a benchmark example.;The subject of this paper is the fault diagnosis of analog circuits based on the use of nullor concept. The fault location technique presented in the paper can be implemented in the general-purpose analysis program which provides many advantages, of which the most important is the automation of the diagnosis process. A simulation based diagnosis model can be obtained by introducing the norators across the potentially faulty elements and the fixators at the accessible nodes. A practical problem that arises when using this nullor diagnosis model is a lack of an efficient procedure for localization of multiple faults. In the proposed diagnosis technique, the online computational requirements are reduced by introducing a diagnosis model that contains accessible nodes only. The diagnosis model is obtained from the original circuit using relationships among the measured voltages and compensated currents of the faulty elements. The proposed faulty location technique is validated on a benchmark example.;The subject of this paper is the fault diagnosis of analog circuits based on the use of nullor concept. The fault location technique presented in the paper can be implemented in the general-purpose analysis program which provides many advantages, of which the most important is the automation of the diagnosis process. A simulation based diagnosis model can be obtained by introducing the norators across the potentially faulty elements and the fixators at the accessible nodes. A practical problem that arises when using this nullor diagnosis model is a lack of an efficient procedure for localization of multiple faults. In the proposed diagnosis technique, the online computational requirements are reduced by introducing a diagnosis model that contains accessible nodes only. The diagnosis model is obtained from the original circuit using relationships among the measured voltages and compensated currents of the faulty elements. The proposed faulty location technique is validated on a benchmark example.

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
ISSN：0925-1030 volume：95 Issue：1 page：173-179
Elwakil, Ahmed
;
Elamien, Mohammed Balla
;
Maundy, Brent
;
Belostotski, Leonid

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.;We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.;We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.